Semiconductor Packaging

Renesas Subsidiary Creates High-Temp QFN-Like Package

2009-03-09T01:23:00.000-07:00

A Renesas Technology subsidiary has developed a thermal dissipation package that supports a wider operating temperature range than conventional QFN packages. The Pro.Quad package has small portions (<1>

Kenji Tsuda, Asia Contributing Editor -- Semiconductor International, 2/17/2009 7:27:00 AM

Renesas Northern Japan Semiconductor Inc. has developed a new thermal dissipation package that is size-compatible with QFN (quad flat non-leaded) packages. The Pro.Quad package features a rear-side metal in the bottom center, and a small protrusion of lead in the four sides and corners. The package attaches to a PCB more closely, leading to effective heat dissipation. The name of the new package comes from the protrusion in the four corners.

Renesas Northern Japan, a subsidiary of Renesas Technology Corp. (Tokyo), created the package with a form that is similar to QFN packages. However, the Pro.Quad package has small portions (<1>

The Pro.Quad is a QFN-like package that can withstand higher temperatures. (Source: Renesas)

Renesas provides three types of Pro.Quad packages: 6 mm square with 36 leads, 8 mm square with 52 leads, and 9 mm square with 60 leads. The lead pitch of 0.5 mm complies with the JEDEC standard, along with a mounted thickness of <1>In general, a heat dissipation metal with plastic resin in the same plane could peel away the resin or generate a gap between the resin and the metal because of a large thermal expansion coefficient difference between the metal and resin. Renesas has studied a wide variety of combinations of base resin, silica filler, mold release agent and other materials, along with the metal design. The metal sheet in the rear surface is part of the leadframe, and is the same material as the leads.

In conventional mold packages, four corners in a package can tend to concentrate stress with temperature cycles, leading to detachment of the package from the board. The new package has four corner metals that easily adhere to the board, leading to higher endurance during the temperature cycles. In a temperature cycle test of -40 to +125°C, the new package achieved >4000 cycles with no failures. Automotive electronics require up to 1500 cycles, and the company targeted double that number: 3000 cycles. In another temperature cycle test of -40 to +85°C, the new package passed 5500 cycles.

The new package also features visible solder joints, while joints in conventional QFN packages are usually invisible. That makes it possible to check the solder fillets in the Pro.Quad package after reflow soldering, Akaki said.

ASE Leads Gartner Packaging Market Share Ranking

2009-03-09T01:19:00.000-07:00

The economic downturn may lead to consolidation in the packaging industry, according to Gartner Inc. analyst Jim Walker. Advanced Semiconductor Engineering managed to pull in more revenue in 2008 than any of its advanced packaging competition -- topping $3.0B.

Sally Cole Johnson, Contributing Editor -- Semiconductor International, 2/25/2009 9:17:00 AM

The economic downturn and the rise in gold prices are putting a double whammy on the packaging industry, according to Gartner Inc. (Stamford, Conn.).

The Top 10 advanced packaging companies garnering market share on Gartner’s just-released preliminary list for 2008 include Advanced Semiconductor Engineering (ASE, Kaohsiung, Taiwan), Amkor Technology (Chandler, Ariz.), Siliconware Precision Industries Co. (SPIL, Taichung, Taiwan), STATS ChipPAC (Singapore), Powertech Technology (Taipei, Taiwan), UTAC (Singapore), ChipMOS Technologies (Hsinchu, Taiwan), King Yuan Electronics (Hsinchu, Taiwan), Carsem (Ipoh, Malaysia) and Unisem (Ipoh, Malaysia).

Two packaging companies can boast revenue >$2B: ASE and Amkor. They’re followed by SPIL and STATS ChipPAC in the >$1B category, and the remaining six companies’ revenues range from ~$250M to $900M. The Top 10 companies’ combined revenue totaled $12.5B in 2008.

That said, the 2008 revenue numbers aren’t pretty, as Jim Walker, Gartner’s research vice president, semiconductor manufacturing, bluntly put it. “And the packaging market will be down much more in 2009,” he added. “In fact, Q4 last year was abysmal — with everyone down 25-30%. Q1 this year doesn’t look much better, and is likely to decrease another 10% or more. Hopefully, this quarter we’ll see the bottom for both the packaging industry and the semiconductor industry. By March, we might see a little bit of growth, but it’s gone down so much during the past four months, it will take a while to recover. Month by month we’ll start to see a growth of maybe 5-8%, then it’ll start pulling up. But we don’t expect that to happen until the second half — if we’re lucky.”

Preliminary market share of the Top 10 SATS companies, based on recent currency exchange rates. (Source: Gartner)

Another big part of the trouble is that capital expenditures on equipment have dried up. “Companies that were spending $300M to $400M on equipment in 2008 aren’t spending even $100M this year,” Walker noted. “Capital expenditures are down 45-50% or more for the semiconductor capital equipment market — whether it’s front-end or back-end.”

Gold pricing hurts

Rising gold prices are also affecting the profitability of packaging companies that do gold bumping or gold wire bonding, because >10% of the raw material costs and revenue are attributed to gold. “Companies are beginning to move to copper, but the majority still use gold,” Walker pointed out. “Packaging companies are closely related not only to unit production, but also raw materials, especially gold.”

Regarding technologies to watch, Walker said the top companies appear to all be focusing in varying degrees on wafer-level packaging (WLP) and through-silicon vias (TSVs) and driving down costs. In the next six to 12 months, he expects to see several new packaging solutions (as opposed to wafer solutions), because packaging is able to respond more quickly to changing market conditions. “Packaging is often an easier route to solve a customer’s problem without a huge R&D cost and the associated long product development cycles. It takes too long and costs more than $30M to develop some of the new ICs, and that’s a lot of money when you can take two die and put them side-by-side or stack them and get to market within two to three months — as opposed to six months to a year for wafer solutions,” Walker said. “Packaging solutions are helping get new products out there faster.”

Unfortunately, the current economic situation is affecting the packaging industry much like the rest of the semiconductor industry — with reports of layoffs, salary reductions and shutdowns for a week to a month becoming increasingly common. Consolidation is also expected. “With all of the economic turmoil, we’ll likely see lots of industry consolidation because there are more than 130 packaging companies in the market,” Walker noted. “Many companies will not be able to survive the next few years. And it’s not just packaging companies. The memory area is being hit extremely hard. When demand shrinks more than 30%, it becomes a real challenge to stay in business. The good news is that people seem to be still demanding more functionality in their handheld devices — Apple iPhone sales actually continue to hold up.”

Intel Maintains Microprocessor Momentum in Q3

2008-11-01T22:26:00.000-07:00

Intel Corp. gained market share in the worldwide microprocessor business in the third quarter of 2008, on both a sequential and a year-over-year basis, padding its lead in the industry, according to iSuppli Corp.

In the third quarter of 2008, Intel accounted for 80.4 percent of global microprocessor revenue, up 0.3 percentage points from 80.1 percent in the second quarter of 2008. The company extended this gain on the year-over-year comparison, growing its share by 1.7 percentage points from the 78.7 percent it held in the third quarter of 2007.

The picture was slightly different at rival Advanced Micro Devices Inc. (AMD), with the company losing share on a year-over-year basis. In the third quarter of 2008, AMD accounted for 12.1 percent of worldwide microprocessor revenue, a decrease of 1.8 percentage points from the 13.9 percent it held in the third quarter of 2007.

However, on a sequential basis, AMD’s short-term position improved, with the company’s share rising 0.1 of a percentage point from the 12 percent it held in the second quarter.

“Intel’s growth is largely due to the strength of its product portfolio in the notebook segment,” observed Matthew Wilkins, principal analyst, compute platforms, for iSuppli. “In the third quarter, Intel achieved a double-positive, producing share growth on both a sequential and year-over basis, while main rival AMD grew in the short term only.”

Due to the sequential decrease in share of the “others” category, Intel and AMD’s share growth in the third quarter came largely at the expense of smaller suppliers. iSuppli believes the increasingly competitive environment resulting from the global financial crisis is the key reason for this.

Q3 not as bad as feared

While there were some signs that PC demand weakened in the third quarter, iSuppli’s early estimates indicate that PC shipments actually reported healthy growth over the third quarter of 2007, up in the region of 12 to 14 percent.

The notebook segment retained its strength and momentum, and continued to be a key growth driver for the PC industry in the third quarter.

iSuppli’s current PC forecast calls for unit growth of 12.5 percent in 2008.

ASE to leverage SUSS MicroTec’s litho equipment in wafer level packaging ops

2008-11-01T22:23:00.000-07:00

By Ann Steffora Mutschler, Senior Editor -- Electronic News, 11/22/2007

Driven by market demands for faster, smarter, portable and integrated electronic products, semiconductor assembly and test services provider ASE Group said this week it will use lithography production equipment from Munich, Germany-based SUSS MicroTec including several production mask aligners and coat/bake/develop clusters for 200 mm and 300mm, in its move towards more sophisticated semiconductor applications.

The equipment is to be installed at ASE’s wafer level packaging and redistribution process facility in Kaohsiung, Taiwan.

The companies reminded that wafer level packaging is an advanced packaging technology whereby the die and package are manufactured and tested on the wafer, then diced into individually packaged ICs.

D.Y. Chen, VP of advanced packaging operations at ASE Kaohsiung said as a result of its more towards more sophisticated semiconductor application, the company has to rely on production equipment that allows high yields, unmatched throughput and cost effectiveness.

Semiconductor Packaging Materials

2008-11-01T22:15:00.000-07:00

SPM is a diverse, world class manufacturer of interconnect solutions for the microelectronics industry. SPM products are currently divided into several product groups: bonding wire and ribbon, precision metal stampings, custom alloyed strip and cladded materials, and a variety of packaging solutions including waffle pack and tape on reel solutions.

SPM's products are assembled, integrated, or bonded to assemblies and subassemblies serving the data and wireless communications, automotive electronics, medical electronics, power semiconductors, microwave and RF, Internet server and European "smart card" industries.


	Fine Gold and Aluminum wire and ribbon

SPM is a leading provider of quality fine gold, aluminum and alloyed wire. This high purity wire is sold to a diverse customer and application usage base including hybrid, medical and automotive electronic packages. SPM's special proprietary wire alloys and doping recipes, combined with its extensive wire manufacturing capabilities in the US, Morocco and Malaysia, make SPM the preferred choice for our global customers.


Stamped metal preforms

SPM's manufactures high precision metal stampings used to solder or connect electronic circuitry, package electronic circuitry, dissipate heat, or provide an interface for an electronic connection. SPM, with its well defined manufacturing process, available capacity, and global manufacturing presence is well positioned to help customers meet their worldwide requirements for precision stampings.


	Tape on Reel product

SPM has perfected a variety of standard and custom packaging including tape on reel, waffle pack, and assorted other special packaging requirements of our customer base. SPM packages its own stampings or the parts of customers and third parties to provide an "automated insertion ready" packaged product. SPM is proud of it's supplier partnerships with companies like Visteon (Ford), Motorola, and Delco. As an example of our customer focus, and our unique three pass, part-orientation detection system, we have recently surpassed one part per billion quality with Delco's tape on reel special pack requirement. Understanding the stringent cleanliness requirements of our customers, SPM operates a Class 10,000 clean room to package its tape-on-reel product line.

Unisem Takes Copper Wire Bonding Process to Volume Production

2008-11-01T22:07:00.000-07:00

by: Semiconductor.net

Unisem Takes Copper Wire Bonding Process to Volume Production

Unisem plans to set up 30% of its wirebonders for copper by 2009. The industry's interest in copper wirebonding is being driven largely by copper's enhanced performance characteristics.

Sally Cole Johnson, Contributing Editor -- Semiconductor International, 10/15/2008 9:23:00 AM

Unisem Group (Kuala Lumpur, Malaysia) is taking its copper wire bonding technology to volume shipment, now that Integrated Device Technology (IDT, San Jose) and several other IC manufacturers have qualified the process. And in response to increasing customer demand, Unisem plans to set up 30% of its wire bonders for copper by 2009.

The industry’s shift from gold to copper wire bonding is being driven largely by the enhanced performance characteristics of copper, such as its high tensile strength, thermal conductivity, lower electrical resistance and better performance during high-temperature storage tests. IDT, for example, recognized the traction copper is gaining as an interconnect material in semiconductor packaging, and is using Unisem’s copper wire bonds in its thin shrink small outline packages. “The clear advantages of copper — better performance and higher electrical test yields — helped convince us of the strategic benefits of copper wire,” said Anne Katz, IDT’s vice president of worldwide assembly and test.

Unisem sees material advantages to using copper wire bonds.

“Copper has turned out to be a key enabler in the packaging industry from both technology and cost perspectives,” pointed out Mike McKerreghan, chief operating officer of Unisem’s Batam, Indonesia, factory. “Today, the most commonly used conductor metals in the IC industry are gold, aluminum, silver alloy and copper. Gold is the most widely used metal for IC wire bonding because of its resistance to surface corrosion and high productivity through the gold ball bonding process. However, the price of gold has risen significantly — by more than 50% during the past 18 months. The upward trend in gold base price has spurred customer interest in gold wire replacement, which helps reduce cost without diminishing conductivity, chip functionality and reliability.”

Aluminum is presently used on discrete/power devices because of its current carrying capacity. “There are two trade-offs, though,” McKerreghan explained. “First, a lower productivity of wedge bonding compared to gold ball bonding. The second is a lack of flexibility to cope with complex wire layouts such as multi-tier and long wire lengths.”

Silver alloy is more conductive than gold and uses the same ball bonding process, according to McKerreghan, but has inconsistent pressure cooker test performance. Copper is also more conductive than gold and is considerably cheaper. “It uses the same ball bonding process with the addition of a forming gas to provide an inert environment during free air ball formation,” McKerreghan said. “Copper/aluminum intermetallics have considerably slower inter-diffusion than gold/aluminum intermetallics, which prevents Kirkendall voiding, ensuring better performance during high-temperature storage tests. Heavy copper wire, ≥2.0 mils in diameter, is already widely used in the industry today for power applications. With these, copper is selected as the most suitable replacement for gold wire.”

Although wire bonding remains the dominant form of interconnect between an IC and package, McKerreghan noted that the industry is beginning to see the need for flip-chip packaging because of the increase in device complexity, as well as being another way to remove the cost of gold from the equation with bumping materials such as copper and solder.

Tape on Reel

2008-06-28T04:12:00.000-07:00

Semiconductor Packaging Materials' patent-pending "Tape-on-Reel" packaging is a value-add process of placing stampings, typically capacitors, resistors, resistor networks and ceramic substrates, onto contact or pocket tape in an automated fashion. The process is used to support surface mount assembly operations, and accomplishes precision parts setting, orientation and handling. Since many of the Semiconductor Packaging Materials' stamped products are very small, Semiconductor Packaging Materials employs the use of highly automated equipment to perform this packaging function.

Prior to loading components on tape - the packaging department works with the customer to determine the proper carrier tape to use. Carrier tape is the tape that "carries" the part. Semiconductor Packaging Materials utilizes two different types of carrier tape - pocket (sometimes referred to as embossed) tape and surf tape. Pocket tape is appropriately described as it is a plastic tape embossed with pockets. During the taping process - the parts are placed in the pocket and then covered using a "cover tape" to keep the parts secure in the pocket. Pocket tape comes in both standard and custom sizes to meet the needs and usage requirements of the customer.

Semiconductor Packaging Materials pays significant attention to the proper selection of both the pocket and cover tapes. Size is one consideration, but other considerations include; the size of the reels, whether anti-static tape is needed, (either pocket or cover) whether conductive or non-conductive tapes are needed (either pocket or cover) and whether the cover tape should be heat or pressure activated.

Semiconductor Packaging Materials uses another form of carrier tape known as surf tape. Surf tape is tape with an adhesive back layer. This back layer holds the part in place without the use of a cover tape. Surf tape works well with small parts where exact orientation is important. By holding the parts with an adhesive - surf tape prevents movement and alignment problems. Surf tape is available in a conductive form.

Semiconductor Packaging Materials offers a variety of reel sizes. Different customers have different reeling requirements depending on the usage of the part, and the type of automated equipment being used. Larger reel sizes typically mean more uptime on the equipment due to fewer changeovers.

Semiconductor Packaging Materials creates custom engineered solutions for tape on reel loading - each customer requirement must be evaluated for the following properties:
Size
Orientation (which side is up)
Anti-Static nature
Conductive properties
Reel Size
Quantity per reel

Semiconductor Packaging Materials' tape on reel packaging offers many advantages to the customer. Semiconductor Packaging Materials taped products are pick and place ready - a perfect solution for high volume, low cost operations. The use of taped products permits exact consumption - eliminating waste, shrinkage and other material losses. Using taped components eliminates the need for capital equipment including shaker tables and other part alignment and orientation devices.

Semiconductor Packaging Materials has built taping capacity around the notion of one-stop shopping for its customers. Semiconductor Packaging Materials is the only US-based company stamping and taping it's own products. One stop shopping means fewer headaches, qualifications, and paperwork for Semiconductor Packaging Materials' customers.

IC Packaging

2007-09-23T09:31:00.000-07:00

The heart of all electronics is the active device, and the ubiquitous active device is the transistor. Virtually all real progress in electronics accures from improvement of the basic device and enabling the use of more and more of them within constraints of size, weight, cost, and energy consumption.

In order for the active device to function, it must be electrically connected to other devices-with physical assurance that the connections will be maintained. Further, the active device must be protected from attack by the environment. Finally, since the active device consumes power to perform its function, heat is generated. Since heat can shorten the life of active devices, a means must be provided to carry the heat away.

To provide these necessary functions of interconnection, physical support, environmental protection and heat dissipation, the active device must be surrounded by or encased in a package. An illustrarion of this concept is presented in Figure 1. Packages may be simple or they maybe complex-depending on the nature of the device, the system of which it is a part and the environment in which the device must operate.

The very surrounding of the active device with protective material, however, can degrade the performance if the device, increase its physical size and weight, make testing the device more difficult and decrease reliability. Moreover, the art of
making the electronic package incure costs-which may be far higher than the cost of the active device itself. Thus, the art of providing an effective electronic package becomes a complex balence of providing desired functions against constraints which may interact among themselves as even further constraints.

As a practical matter, the IC manufacturer must decide whether to package a given IC in one or more standard packages (nesessary for merchant sales) or develop one unique to its needs (giving it a systems advantage over its competitors). We will confine our discusions to "standard" types, however.

What is wire bonding

2007-09-16T06:43:00.000-07:00

Wire bonding is a method of making interconnections between a microchip and other electronics as part of semiconductor device fabrication.

The wire is generally made up of one of the following:

Wire diameters start at 15 µm and can be up to several hundred micrometres for high-powered applications.

There are two main classes of wire bonding:

Ball bonding usually is restricted to gold and copper wire and usually requires heat. Wedge bonding can use either gold or aluminium wire, with only the gold wire requiring heat.

In either type of wire bonding, the wire is attached at both ends using some combination of heat, pressure, and ultrasonic energy to make a weld.

Wire bonding is generally considered the most cost-effective and flexible interconnect technology, and is used to assemble the vast majority of semiconductor packages.

Category: Sem

What is Flip Chip

2007-09-11T08:53:00.001-07:00

What is Flip Chip?

Flip Chip (FC) is not a specific package (like SOIC), or even a package type (like BGA). Flip Chip describes the method of electrically connecting the die to the package carrier. The package carrier, either substrate or leadframe, then provides the connection from the die to the exterior of the package. In "standard" packaging, the interconnection between the die and the carrier is made using wire. The die is attached to the carrier face up, then a wire is bonded first to the die, then looped and bonded to the carrier. Wires are typically 1-5 mm in length, and 25-35 µm in diameter. In contrast, the interconnection between the die and carrier in flip chip packaging is made through a conductive "bump" that is placed directly on the die surface. The bumped die is then "flipped over" and placed face down, with the bumps connecting to the carrier directly. A bump is typically 70-100 µm high, and 100-125 µm in diameter.

The flip chip connection is generally formed one of two ways: using solder or using conductive adhesive. By far, the most common packaging interconnect is solder Current solder types are: eutectic (63%Sn, 37%Pb) or high lead (95%Pb, 5%Sn) or lead-free (97.5%Sn, 2.5%Ag) compositions. The solder bumped die is attached to a substrate by a solder reflow process, very similar to the process used to attach BGA balls to the package exterior. After the die is soldered, underfill is added between the die and the substrate. Underfill is a specially engineered epoxy that fills the area between the die and the carrier, surrounding the solder bumps. It is designed to control the stress in the solder joints caused by the difference in thermal expansion between the silicon die and the carrier. Once cured, the underfill absorbs the stress, reducing the strain on the solder bumps, greatly increasing the life of the finished package. The chip attach and underfill steps are the basics of flip chip interconnect. Beyond this, the remainder of package construction surrounding the die can take many forms and can generally utilize existing manufacturing processes and package formats.

Benefits of Flip Chip:

Using flip chip interconnect offers a number of possible advantages to the user:

Reduced signal inductance - because the interconnect is MUCH shorter in length (0.1 mm vs 1-5 mm), the inductance of the signal path is greatly reduced. This is a key factor in high speed communication and switching devices.

Reduced power/ground inductance - by using flip chip interconnect, power can be brought directly into the core of the die, rather than having to be routed to the edges. This greatly decreases the noise of the core power, improving performance of the silicon.

Higher signal density - the entire surface of the die can be used for interconnect, rather than just the edges. This is similar to the com parison between QFP and BGA packages. Because flip chip can connect over the surface of the die, it can support vastly larger numbers of interconnects on the same die size.

Die shrink - for pad limited die (die where size is determined by the edge space required for bond pads), the size of the die can be reduced, saving silicon cost.

Reduced package footprint - in some cases, the total package size can be reduced using flip chip. This can be achieved by either reducing the die to package edge requirements, since you no longer have to leave space for wires, or in utilizing higher density sub strate technology, which allows for reduced package pitch

Single Element Semiconductors

2007-03-17T03:26:00.000-07:00

Silicon, Si - the most common semiconductor, atomic number 14, energy gap Eg = 1.12 eV - indirect bandgap; crystal structure - diamond, lattice constant 0.543 nm, atomic concentration 5x1022 atoms/cm-3, index of refraction 3.42, density 2.33 g/cm3, dielectric constant 11.7, intrinsic carrier concentration 1.02 x 1010 cm-3, mobility of electrons and holes at 300 K: 1450 and 500 cm2/V-s, thermal conductivity 1.31 W/cm-oC, thermal expansion coefficient 2.6 x 10-6 1/oC, melting point 1414 oC; excellent mechanical properties (MEMS applications); single crystal Si can be processed into wafers up to 300 mm in diameter.
Ge, C, Sb.

Silicon on Insulator (SOI)
Only a thin layer on the surface of a silicon wafer is used for making electronic components; the rest serves essentially as a mechanical support. The role of SOI is to electronically insulate a fine layer of monocrystalline silicon from the rest of the silicon wafer. Integrated circuits can then be fabricated on the top layer of the SOI wafers using the same processes as would be used on plain silicon wafers. The embedded layer of insulation enables the SOI-based chips to function at significantly higher speeds while reducing electrical losses. The result is an increase in performance and a reduction in power consumption. There are two types of SOI wafers. Thin film SOI wafers have a device layer <1.5>1.5 ?m.
Wafer bonding. - In this process the surface of two wafers are coated with an insulating layer (usually oxide). The insulating layers are then bonded together in a furnace creating one single wafer with a buried oxide layer (BOX) sandwiched between layers of semiconductor. The top of the wafer is then lapped and polished until a desired thickness of semiconductor above the BOX is achieved.
SIMOX - Seperation by Implantation of Oxide. In this process a bulk semiconductor wafer is bombarded with oxygen ions, crating a layer of buried oxide. The thickness of intrinsic semiconducor above the box is determined by the ion energy. An anneal reinforces Si-O bonds in the BOX.
Smart Cut - The wafer bonding method is used to form the BOX, but instead of lapping off excess semiconducor (which is wasteful) a layer of hydrogen is implanted to a depth specifying the desired active layer of semiconductor. An anneal at ~500oC splits the wafer along the stress plane created by the implanted hydrogen. The split wafer may then be reused to form other SIO wafers.

Semiconductor Packaging Goes Vertical

2007-02-19T03:15:00.000-08:00

Stacked packaging gets more silicon in less space
Randy Frank, Contributing Editor -- Design News, June 5, 2006

When Nokia and Amkor Technology discussed 3D packaging roadmaps five years ago, the stage was set for a new packaging solution for logic plus memory integration. Today known as Packaging on Packaging or PoP, the 3D solution addresses a wide range of multimedia applications to integrate digital baseband, application or image processors with high capacity or combination memory devices. By dealing directly with the system supplier, Amkor gained a better understanding of the total requirements (technical, business and logistical) necessary to develop a highly successful product and supply chain infrastructure. The benefits of PoP are being widely recognized in portable applications as PoP is being designed into digital cameras, portable medial players and mobile gaming, in addition to mobile phones.

The industry shift to smart phones with new multimedia features such as web access, camera, video, music and gaming requires a huge increase in processing power and memory capacity. To integrate these costly new features with an expanding processor and memory architecture, the size, weight and cost reduction trends for mobile phones flattened or reversed. The market pays a premium for the right features and functions in innovative form factors. To achieve the design flexibility and cost objectives phone designers have turned to PoP to solve their logic + memory integration challenges, as there are multiple advantages in stacking the memory right on top of the processor.

Previously this stacking was done at the package level with die stacked in a single package. However, stacked die integration has several technical and business issues to overcome. "The processor suppliers are not in the memory business and the memory suppliers are not in the logic business, the business model for stacked die is horrible from all perspectives," says Lee Smith, senior director business development, Amkor Technology.

The method of die stacking known as System in Package or SiP, integrates one or more memory devices into a single package sold by the processor supplier. This approach requires two competing companies to cooperate. The memory supplier has to provide known or near good die in wafer form at near commodity prices and absorb much of the risk for final yields, test and lost revenue from not quite good enough devices on the wafer. From the business perspective, this approach is not flexible or cost-effective for the OEM when sourcing, time to market, design changes and total cost of ownership are taken into account.

To develop the new package stack, Amkor did the package design, development and qualification while Nokia did the package stacking and board level solder joint qualification as reported at ECTC in 2003. Once the PoP was pre-qualified, it was designed into an innovative new phone form factor and specified to the processor and memory semiconductor suppliers to deploy in production.

How PoP Stacks Up

Amkor's high density package stackable very thin fine pitch BGA (PSvfBGA) bottom package combines the capabilities from well established package technology platforms: thin stacked die capability with low loop wire bonding and etCSP's (Extremely Thin Chip Scale Package) advanced center pin gate molding on four layer (1-2-1) high density laminates to handle the high wiring density and crossing memory circuits. The top overmolded FBGA package with solder balls around the periphery contains the memory chips and surface mounts directly on top of the bottom package straddling the logic chip. The same or similar lead-free alloy solder balls are used on the top and bottom so the stack reflows uniformly during surface mount board assembly. The packages come together during the final assembly process allowing the OEM to control its device integration. Up to that point, there is flexibility to mix and match the top and bottom devices and preferred suppliers as required. The PoP structure is an open platform with JEDEC standards in place for the design guide, mechanical outlines and various memory pin outs across a range of package sizes.

A key objective in JEDEC and in PoP adoption is defining a flexibly memory interface that supports multiple memory combinations and is supported by all the key memory suppliers as a standard. These standards enable the logic supplier to better floor plan her processor's memory controllers and interconnect interface as a design for stacking which can reduce the package wiring density to reduce cost and improve electrical performance. Current processors are designed for CSPs to interface to a memory Multi-Chip Package (MCP) adjacent on the mother board, as a result the memory interface bond pads are on one side of the chip which pushes wiring density into the bottom logic package to reroute the crossing memory circuits from the top four-sided package

To deploy PoP stacks in high volume, a key design challenge is controlling warpage of the bottom package across high temperature lead-free solder reflow profiles. As a result, the mold compound for the top and bottom packages are not necessarily the same. Because the bottom package has an unbalanced construction, the compound is specifically selected for warpage control. "When you mold all the way to the package edges and saw singulate like the top MCP, that's much easier to control warpage and coplanarity," says Smith. "With the unbalanced package, the substrate is thicker than the mold cap, so the coefficients of thermal expansion (CTE) and modulus of elasticity of the materials become more important."

Another key aspect to address warpage was shifting the industry from looking at room temperature coplanarity as the critical criteria for incoming inspection. Since the warpage factors with two packages are most critical at the liquidus temperature where the two units solder together, this changed to characterizing the two packages together for the warpage profile across the reflow temperature profile. This shift in industry thinking has proven to be effective. "Stacking yields are being reported from OEMs at high levels matching what they get with 0.5 mm CSP assembly," notes Smith.

Upward and Onward

The first PoP stack for cellphones went into production in October 2004. The PoP stack had four elements in the top package — SDRAM, NOR and NAND die plus a spacer. "When you get to complex four and five stacks with low cumulative die yield and high die and test cost, then PoP overwhelmingly becomes the lowest cost solution," says Smith.

The outlook for the market acceptance for PoP products is extremely good. Jan Vardeman of market research company TechSearch International forecasts 300 million packaging stacks for 2007. Part of this optimism is based on equipment suppliers either optimizing or retrofitting their equipment for package stacking. "The EMS/OEM guys are quickly coming on board," says Smith. "Flextronics has been doing this in high volume assembly for a couple of years. By next year this will become a dominant technology for logic plus memory integration."

Contact: Lee Smith, senior director business development, Amkor lsmit@amkor.com

Hermatic Semiconductor

2007-02-10T06:52:00.000-08:00

The present invention is directed to several embodiments of a hermetically sealed semiconductor package. One embodiment is constructed from a substrate of a first copper alloy, a cover member of a second copper alloy and a lead frame of a third copper alloy. A low melting point sealing glass composite is disposed between the cover member and the substrate for sealing the lead frame therebetween. The third copper alloy is precipitation hardenable and has excellent softening resistance at glass sealing temperatures as compared with other conventionally used alloys. In another embodiment, a clad composite having a core of the third copper alloy and cladding layer of a copper alloy having a low oxidation rate may be advantageously used for the lead frame

Semiconductor Package

2007-02-10T06:34:00.000-08:00

Abstract

A semiconductor package for mounting a chip is disclosed. The package includes a first metal or metal alloy component having a first thin refractory oxide layer on a first surface. The chip is bonded to the first component. A skirt extends from the first component for strengthening the first component and providing heat transfer from the semiconductor package. A second metal or metal alloy lead frame having second and third refractory oxide layers on opposite surfaces is electrically connected to the chip and is bonded to the first oxide layer. Also, the lead frame is insulated from the first component by the first and second refractory oxide layers. A second metal or metal alloy component has a fourth refractory oxide layer on one surface and is bonded to the third refractory oxide layer so that the chip is hermetically sealed between the first and second components. Other embodiments of the present invention include both leadless and leaded hermetic semiconductor packages...